YOU ARE AT:Chips - SemiconductorIntel to acquire eASIC

Intel to acquire eASIC

Intel picks up structured ASIC chip maker

Intel is beefing up its portfolio of chips with the purchase of eASIC, a fabless designer of application-specific integrated circuits (ASICs). Founded in 1999, eASIC makes a version of the ASIC called a structured ASIC. The structured ASIC has elements of both ASICs and field programmable gate arrays, with a more FPGA-like architecture.

“Having a structured ASICs offering will help us better address high-performance and power-constrained applications that we see many of our customers challenged with in market segments like 4G and 5G wireless, networking and IoT,” said Intel’s Dan McNamara, corporate vice president and general manager of the Programmable Solutions Group (PSG), in a blog post. “We can also provide a low-cost, automated conversion process from FPGAs (including competing FPGAs) to structured ASICs.“

The FPGA is a chip that can be erased and reprogrammed after being manufactured, unlike the standard cell ASIC, which is designed — usually at great cost — to work optimally for a specific device. The FPGA has become a popular prototyping tool but doesn’t have the power optimization of an ASIC.

The structured ASIC is cheaper to build than a full-blown ASIC, because it adds a modifiable layer on top of base ASIC layer. In a 2006 article, an author from FPGA-maker Altera (now part of Intel) explains encouraged designers to make a devices that worked with either the structured ASIC works or the FPGA. At the time, Altera had its own structured ASIC, called Hardcopy. In 2015, Intel purchased Altera, one of the two main FPGA vendors at the time.

Intel is putting eASIC into its Programmable Systems Group. Intel says it expects to close the deal in third quarter of 2018. Financial terms of the deal have not been disclosed.


Susan Rambo
Susan Rambo
Susan Rambo covers 5G for RCR Wireless News. Prior to RCR Wireless, she was executive editor on EE Times,,, Planet Analog and EBNOnline. She served also EE Times’ editor in chief and the managing editor for Embedded Systems Programing magazine, a popular how-to design magazine for embedded systems programmers. Her BA in fine art from UCLA is augmented with a copyediting certificate and design coursework from UC Berkeley and UCSC Extensions, respectively. After straddling the line between art and science for years, science may be winning. She is an amateur astronomer who lugs her telescope to outreach events at local schools. She loves to hear about the life cycle of stars and semiconductors alike. She is based in the San Francisco Bay Area. Follow her on Twitter @susanm_rambo.

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