RCR ran into Cadence at the Common Platform Technology Forum in Santa Clara this week and talked to the firm about its role in the collaborative manufacturing effort.
Cadence, IBM, GLOBALFOUNDRIES and Samsung have collaborated and developed several generations of reference flows for the Common Platform.
These reference flows are based on the Cadence Encounter digital IC design platform and are targeted to the Common Platform processes.
The reference flows use a wire-centric methodology to address key 65nm and below SoC issues including low-power design, signal integrity, and design-for-manufacturing to provide high quality of silicon (QoS) – using metrics of power, performance and area.
Cadence has also just announced the availability of its upgraded EDA tools for the 28-nanometer(nm) high-k metal gate(HKMG) technology from the Common Platform alliance.
Cadence says its new Silicon Realization reference flow for the alliance is built around its Cadence end-to-end Encounter flow, including Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and Encounter Power System.
It was validated using the 32/28-nanometer ARM low-power physical libraries, and employs the Common Power Format (CPF)-enabled Cadence Low-Power Solution to maintain power intent throughout the design process.
Check out the video below for a better explanation.
