Chip manufacturers band together at Common Platform Technology Forum

The devil is in the details, especially when it comes to working on a microscopic nanometer scale – that was the main message from executives from GlobalFoundries, Samsung and IBM on Tuesday at the Common Platform Technology Forum in Santa Clara.
The firms, bound together under the umbrella of IBM’s fab alliance work as a common platform effort to counter the powerful TSMC and Intel chip making block, and believe they are stronger and more efficient as a team, even though competition for customers can be tricky.

“It’s a lot of fun,” said Globalfoundries’ COO Chia Song Hwee, quickly adding, “I don’t want to trivialize the effort. It certainly takes a lot of commitment to make sure this model works. We do have common customers and we have to be competitive to get our fair share of the business. That means we have to excel at multi-faceted relationships, and that takes commitment, execution, and a lot of work.”
The Co-opetition model, added Stephen Woo, Samsung’s president of the System LSI Division, could only truly be achieved with an abundance of trust and drive from top down. “So far we have not seen any problems and I hope we can continue this collaboration,” he said.
“The enemy is not here, it is on the other side,” Song Hwee chimed in, noting that the trend in the industry was still strongly leaning towards a collaborative manufacturing model, not only in the US, but in Europe and Asia too. Wireless buffs will also be pleased to note that Qualcomm has also pledged its support to the fab cooperative model.
The reasons for this were financial as much as practical, with new 28nm chip manufacturing costs estimated to be around $50 million in development and base designs alone, plus another $250 million to build libraries for the chip. If that wasn’t steep enough, building a new fab to make the chip in would cost $5-$7 billion, with an additional $1-$2 billion in development costs over the subsequent four years. Not the kind of liquid cash available to most individual firms, but much easier as a team effort.

R&D is also made abundantly easier as a group, with technologies like High-K Metal Gate to prevent leakage and increase chip power efficiency taking over a decade to develop and integrate into the manufacturing process. And with every subsequent shrink, the firms are actively looking at new technologies like like silicon nanowires, phase change memory and silicon photonics to keep pace.
“32nm and 28nm is now being delivered,” said VP of IBM’s R&D center Gary Patton adding that the alliance has worked through the issues of integrating high K metal gate and that 20nm was coming up quickly.
“It’s amazing the depth and breadth of the R&D we have and the extent of the scalability we have from the previous node,” he added. Indeed, Patten claims the alliance saw a 6% power and performance benefit using its celebrated High K Metal Gate gate first approach, though he insisted a switch to gate last was imperative for 20nm and beyond.
“We just focus on delivering the best solution to our customers, and we’re agnostic about what that solution is,” he said, presumably to those critics accusing the alliance of flipflopping from gate first to gate last technology, seen by some as a validation of Intel and TSMC’s methods.
The main upcoming issues, the panel agreed, would be those of capacity, and when chips were going to be ready. “2012 very much depends on demand,” noted Woo, adding that Samsung was very focused on low powered smart devices, which were currently booming. “That translates into higher demand, so we expect a tight 2011 and probably that will continue into 2012,” he said.